Visual display system

ABSTRACT

A constant writing rate vector generator capable of accepting digital inputs representative of the endpoints of a line and converting them into analog voltages proportional to the transition time of the generated line such that random positioning of the electron beam on a cathode ray tube and the writing of vectors while maintaining an equal and constant brightness without additional intensity compensation is achieved. The digital endpoint data controls a constant voltage ramp with a time duration directly proportional to the vector length, which ramp is used to control the transition rate of a pair of digital to analog converters.

United States Patent Apr. 3, 1973 Bleiweiss [54] VISUAL DISPLAY SYSTEM[75] Inventor: Mark H. Bleiweiss, Marlboro, Mass.

[73] Assignee: Raytheon Company, Lexington,

Mass.

[22] Filed: Jan. 20, 1971 [21] Appl. N0.: 107,930

[52] US. Cl. ..340/324 A, 235/151, 315/18,

[51] Int. Cl. ..G06t 3/14 [58] Field of Search ..340/324 A; 328/183,185; 315/18, 26; 235/151 [5 6] References Cited UNITED STATES PATENTSPrimary Examiner-David L. Trafton AttrneyMilton D. Bartlett, Joseph D.Pannone, Herbert W. Arnold and David M. Warren [57] ABSTRACT A constantwriting rate vector generator capable of accepting digital inputsrepresentative of the endpoints of a line and converting them intoanalog voltages proportional to the transition time of the generatedline such that random positioning of the electron beam on a cathode raytube and the writing of vectors while maintaining an equal and constantbrightness without additional intensity compensation is achieved. Thedigital endpoint data controls a constant voltage ramp with a timeduration directly proportional to the vector length, which ramp is usedto control the transition rate of a pair of digital to analog 3,320,409/1967 Larrowe ..340/324 A X onverter 3,482,309 12/1969 Bouchard...340/324 A X I 3,325,802 6/1967 Bacon ..340/324 A 4 Claims 7 Drawin Fiures 2a [2 r N n I N n 3 t X0 X E Z Xon X0 (XODVOVUREOZ X V l-,,. -Xo ila) 'REcIsTER D/A a f t X susgAcrIoN Axojzmorrxm) SUMQING \OUT('):)(AU-tqV) N WORK me illx CHANNEL ,XOUXIDWD AMPLIFIER N 22 X I DVI M12 5 /4 X v 'c I I In ref 11 R IsT R /A 2 g 56 x 2" D 1A Q C(Y lS"TlWTRKTE UIW-I" I GENERATOR I q LENGTH V t) CALCULATOR RAMP I l INVERTER V(t) DISPLAY z I Ax +AY GENERATOR I rer" 0 3 I LUD 42 I E I 48 I 52 0 N 0l6 n i E L, "I x 'n o Yln Y1 Y V ttl-Y REGISTER D/A suBTRAcrIoN N YNETWORK SUMMING Y CHANNEL lip- D|=AYD AY i2 (Y -AMRI IFIER our oA E 2434 lAT 1a t l Y YO OD d QA TI REGISTER l N W 4 Z'W PATEi-HWAPM m5 SHEET5 0F 5 304 m o wom qzo C F l|.| :9: m3 M936 VISUAL DISPLAY SYSTEMBACKGROUND OF THE INVENTION This invention relates to graphic visualdisplay systems and more particularly to a vector generator suitable foruse in a computer controlled stroke or vector generation system.Computer controlled stroke generating systems utilizing cathode raytubes of the prior art have inherent inaccuracies resulting fromvariable writing speeds, and require brightness compensat-' ing circuitsto compensate for the reduced illumination produced by long vectorswhich must be written in the same time as short vectors. It is thereforedesirable to write at a constant rate, independent of vector length toeliminate compensating circuitry and to improve overall system accuracywhen many strokes must be generated.

A constant writing rate vector generator is disclosed by patent Ser. No.3,482,086 to CF. Caswell and assigned to the same assignee as thepresent application. Constant writing rate is achieved by means of anerrorrate processor which developes an error voltage function inorthogonal axes. These orthogonal X and Y error voltages are summed inquadrature, normalized and separated into X and Y components to developa continuous calculation for the composite error voltage. In the presentapplication, digital endpoint data is coupled directly from a computerto derive an approximate length calculation which controls a rampgenerator to generate control voltages proportional to the vectorlength. The charging and discharging of a bank of hinary weightedcapacitors generates the required ramp function, and the balancedmodulators and demodulators, the normalization circuitry and the errorprocessor of Caswell is eliminated.

SUMMARY OF THE INVENTION The above and other features and advantages ofthe present invention are achieved by the provision of a constantwriting rate vector generator in which digital endpoint data in twoorthogonal axes is coupled directly from a computer or interfacecircuitry to a vector length calculator and to a pair of data decoderswhich determine the vector direction and endpoints. A constant rate rampgenerator comprising a plurality of binary weighted and digitallycontrolled capacitors generates a constant voltage ramp with a timeduration directly proportional to the vector length. The ramp is used asa reference for a pair of digital-to-analog converters in each axis todirectly control the transition rate of the digital-to-analog converter,thereby providing analog outputs controlling the constant transitionrate proportional to the vector length between the vector coordinates.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an operational block diagramof a stroke generator in accordance with the present invention;

FIG. 2 is a diagram of several of the outputs of the circuitry describedby FIG. I for one axis;

FIG. 3 is a block diagram of the vector length calculator of the presentinvention;

FIG. 4 is a block diagram of an embodiment of the stroke generator ofthe present invention;

FIG. 5 is a simplified circuit diagram of the ramp generator employed inthe embodiment illustrated by FIG. 4;

FIG. 6 is a simplified circuit diagram of the switching circuitryemployed with the ramp generator of FIG. 5; and

FIG. 7 is a waveform diagram of the timing waveforms required tointerface the stroke generator of the present invention with a centralcomputer.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, avector generator is illustrated generally at 10 which has the capabilityof accepting digital inputs representing the end points of a line andconverting them into analog voltages representing the transition orwriting time of the line. Equal and constant brightness withoutintensity compensation with random positioning of the electron beam isachieved.

Positional data from a central computer or data on input lines such astelephone lines is inputted to the vector generator 10 via data linesl2, l4, l6 and 18 to two X axis positional storage registers x and X 20and 22, respectively, and to two Y axis positional storage registers Yand Y,, 24 and 26, respectively. The positional data inputted toregisters 20 through 26 comprises the X and Y line end point data indigital form. The outputs of X registers 20 and 22 are fed todigitalto-analog converters 28 and 30 respectively, the analog outputsof which are summed in an X position summing amplifier 32. Similarly,the outputs of Y registers 24 and 26 are fed to digital-to-analogconverters 34 and 36, respectively, the analog outputs of which aresummed in a Y position summing amplifier 38. The X and Y summingamplifier outputs supply constant rate transition signals to theelectron beam deflection circuitry of a CRT at a constant writing rateas will be described with reference to FIG. 4 (calculator) 40 forpositioning the electron beam in the X and Y axes.

The line length is calculated from the digital end points in a lengthcalculator network 42 which is supplied with the changes in the X and Yend point coordinate data from subtraction networks 44 and 46,respectively, which provide the absolute values of the X and Y linevariations. The hypotenuse calculation performed in calculating network42 is used to directly control the transition time or the time requiredto generate a ramp voltage between two predetermined limits, one ofwhich is zero and the other of which is a reference voltage Vr in a rampgenerator 48. The length calculator 42 and ramp generator 48, takentogether, comprise the constant rate line generator 50, which will bedescribed in detail, particularly with reference to FIG. 3.

The output of ramp generator 48, which represents the signalperiodicity, or the stroke time duration, is coupled through an inverter52 to the X and Y initial condition digital-to-analog converters 28 and34 and directly to the digital-to-analog converters 30 and 36 whichreceive the X and Y positional end point data for the conclusion of astroke.

The digital end point data inputted to registers 20 through 26 generatesan analog output positional signal representative of stroke length whichis independent of the positioning of the previous stroke, therebyproviding for random access operation. This is accomplished bymultiplying the previous digital number X by zero (0) and the currentnumber X, by a reference voltage Vr to obtain an output which equals X(0) X, (Vr), and (Y 0 Y, (Vr), or X, (Vr) and Y, (Vr). The current wordthen shifts to the X and Y registers and X and Y are inputted to the X,and Y, registers. Thus, X, and Y, are multiplied by zero, hence X, andY, are also independent of the previous position.

Considering only the X channel, as the Y channel is identical, the rampgenerator 48 is at zero (0) and the inverter 52 output is at Vr,therefore the output of register is a digital X and the outputof'digitaI-toanalog converter 28 is X (0) 0; while the output ofregister 22 is a digital X, and the output of digital-to analogconverter 30 is X, Vr f (X and the output of summing amplifier 32 is X,Vr, an analog signal represented as X At time t the first data pulse isloaded into register 20, and at time t,, the second data pulse is loadedinto the X, channel. At time the third data pulse is transferred both tothe X channel, and so forth. Mathematically, at time t=0, a digital wordrepresenting the initial stroke position in the X axis, X is loaded intothe X register. This word, digitally is A new digital word representingthe X, position,

is then loaded into the X, registers, with the ramp generator outputequal to 0 (V, 0) and the inverter output V Vref. Therefore, the summingamplifier output X consists of the analog value X of the digital wordX(X,,,,, X The output of the line length calculator 42 sets the slope ofthe controlled ramp generator 48 such that the stroke transition timeYis directly Proportional to the line length L Referring nowto FIG. 2, atransition time diagram for stroke positioning in the X axis isillustrated. At time i=0, the ramp generator output V,(t), shown ascurve A, increases from zero to the reference voltage, Vref while theinverter output, V,,(t), shown as curve B, decreases from Vrefto zero(0). Simultaneously, the X digital-to-analog converter output X V 0),shown as curve C, decreased from X, to 0 and the X, digital-toanalogoutput, curve D, increases from zero (0) to X, Thus, the final summingamplifier output X transfers from a first analog voltage X to a secondanalog voltage X,,, in a time (Y,,) which is proportional to thecalculated vector line length Ly where:

Referring now to FIG. 3, the circuitry for implementing the vector linelength calculation is illustrated. The length calculator receives, thevector end points in digital form, X X,, Y and Y,, and performs amathematical computation to derive an approximation of the vectorlength, which approximation is used to directly control the rampgenerator transition time for the ramp generator discussed with respectto FIG. 5. I

The vector end points X and X, are fed to a subtractor which derives theabsolute digital value of the difference between X and X whilesimultaneously, the vector end points Y and Y, are fed to a subtractor62 which derives the absolute digital value of the difference between Yand Y,. These values A X and A l are coupled to gating circuitry 64 andto a comparator 66 where the relative magnitudes of A X and A Y arecompared. [f A X is greater than or equal to A Y, A Y is gated into theshift register 68 where it is multiplied by one-half and A X is gateddirectly to an adder 70. Thus, when A X is greater than or equal to A Y,the quantities A Y and A X are inputted to adder 70. If A l is greaterthan A X, A X is gated into the shift register 68 where it is multipliedby one half and A Y is gated directly to the adder 70. Thus, when A Y isgreater than AX, the quantities A A X and A Y are inputted to adder 70.

The above-derived quantities comprise an approximation of thePythagorean quantity VX 7 and the relationship may be expressedgenerally as:

The error due to this approximation is a function of the vector angle,which results in a worst case brightness deviation of approximately plusor minus 6 percent which is imperceptable to the viewing eye.

The calculated approximate vector length, either A X k A Yor A Y+ it A Xis coupled to a storage register 72 from where it is coupled in a binarysequence to the ramp generator 48 described with reference to FIG. 5.

Referring now to FIG. 4, a stroke generator embodying the presentinvention is shown generally at 100. Digital inputs representative ofvector end points are coupled from a central computer (not shown) todata storage registers for the X and Y axes via lines 102 and 104,respectively. The data storage registers which receive the X axisendpoint data are ten bit storage registers 106 and 108, with register106 receiving the vector starting point data and register 108 receivingthe vector end point data in the X axis. Similarly, for the Y axis, 10bit storage registers 110 and 112 receive the Y axis starting and endpoint data respectively. A total of 40 bits of X and Y starting andendpoint data is received, with additional bits for blanking, unblankingand intensity, bringing the total required digital input to 43 bits perstroke. The X and Y endpoint data is transferred to the lengthcalculator and to the X and Y axis data decoders 114 and 116,respectively. One bit unblanking signals are coupled from the computerto a one bit storage register, the Z register 1 18 to unblanking logic120, which is a series of AND/OR gates of conventional design, theoutput of which is coupled to the video circuitry of a CRT display in aconventional manner. The length calculator determines the vector lengthwhile the data decoders determine the vector endpoints and direction.

The output of the length calculator 42 is coupled to a constant rateramp generator 122 which generates a constant voltage ramp with a timeduration directly proportional to the vector length. This ramp voltageis used as a reference for a pair of differential digital-toanalogconverters 124 and 126 for the X axis and Y axis respectively; hence,the transition rate of these D/A converters is controlled by theconstant rate ramp generator and by the output of an inverter 128 whichsupplies the inverted output of ramp generator 122, a negative goingramp, to the digital-to-analog converters 124 and 126, The outputs ofthe digital-to-analog converters 124 and 126, which represent thecoordinates of the generated vector, are generated for a timeproportional to the vector length, i.e., the vector transition rate isconstant; hence, the CRT brightness of a display 128 is constant. The Xand Y D/A outputs are coupled to X and Y deflection amplifiers (notshown) in the display, while the Z output, or unblanking signal, iscoupled via line 130 to the video amplifier of the display.

The vector generator control logic circuitry 132 interfaces a centralcomputer and couples the required timing and control signals to and fromthe computer to the X and Y registers and to the ramp generator.

Referring now to FIG. 7, the waveform timing diagram illustrates thevarious timing pulses required. The basic system timing is provided by a100 nanosecond clock illustrated by waveform (a) of FIG. 7. A dataavailable signal is sent from the computer to the logic 132 whenever theinterface circuitry is ready to accept data and when the vectorgenerator is not busy generating previous vectors. This signal,illustrated by waveform (d) is present when an control counter ofconventional design has counted to L9 microseconds.

When the data available signal goes high, an internal state counter witha 100 nanosecond clock initiates data storage and timing signals for thearithmetic length calculation. Waveform (e) illustrates 19 states forthe control counter; however, other states may be added or omitted asdesired.

When the vector generator is processing or writing, a busy signalillustrated by waveform (c) goes high on the first clock pulse after adata available" signal goes low on the trailing edge of a 100 nanosecondend of stroke signal illustrated by waveform (b) indicating the end of avector. New vector generation data cannot be entered while the busy"signal is high. The end of stroke pulse of waveform (b) signals the endof a vector when the vector is completed. This pulse may be generated bya comparator operating in conjunction with a digital one shotmultivibrator to generate the 100 nonosecond pulse.

' A toggle signal illustrated by waveform (j) toggles on every end ofstroke signal to distinguish between successive vectors. Thisdistinction is required since the digital-to-analog converters requirethat the timing of one vector is determined by a positive going ramp andthe timing of the next vector is determined by a negative going ramp,both of which ramps require different control signals. When the nextdata available" signal is received from the computer, the toggle signalswitches from high to low, and during successive states of aconventional state counter, data is strobed into A registers and Bregisters, the X and Y start registers and the X and Y end registers,the timing of which is illustrated by waveforms (k) and (1),respectively. Also, the high and low pulses for charging the binaryweighted capacitors of the ramp generator via the initializingtransistors, as described with reference to FIG. FIG. 5, are generatedon the control count after data is strobed into the X and Y registers asillustrated by waveforms (m) and (n Thus, if on control count 1, data isstrobed into the X and Y start registers, on the rising edge of controlcount 2, the charge capacitors high signal of waveform (m) goes high,thereby insuring that all the capacitor are charged to a fixed positivereference voltage and ready to be linearly discharged causing a negativegoing ramp. The current switch is enabled and goes high to providenegative current to the positively charged binary weighted capacitors inthe proper sequence. This pulse is shown by waveform (g), and it iscoupled to an FET switch as shown with reference to FIG. 5.

At the end of the counting sequence, the length calculation is completedand the analog circuitry is enabled to paint the derived vector. A readysignal, illustrated by waveform (h), is derived from the decoders 1 l4and 116 which is coupled from the logic 132 to the computer, which, uponreceipt of the ready" signal, couples back to the logic a start signalillustrated by waveform (i) to paint the vector. The start" signallowers the ready signal and resets the charge capacitors high signalthereby allowing the capacitors to discharge linearly to ground throughthe current switch. A length enable signal, waveform (f) is generatedwhen the data available" signal is high to implement the vector lengthcalculation.

Blanking of the cathode ray tube beam for vector segments not to bepainted is accomplished by the coupling of a one bit blanking signal,either a logical one or a zero from the computer to the one bit storageregister 118 for input to the unblanking circuits 132, where theunblanking pulse is conventionally processed in the unblanking logic 120before coupling to the video circuits via line 130. Unblanking timing isprovided by the outputs of two voltage comparators, one of which,comparator 134, detects when the generated ram exceeds zero (0) volts,and the other of which, comparator 136, detects when the generated rampreaches the reference voltage Vr. The outputs of comparators 134 and 136are logically ANDed with the unblanking Z bit to produce the vectorunblanking signal when the generated ramp is between zero (0) volts andthe reference voltage Vr when the Z bit is a logical one.

The four-position switches 140 and 142 for the X and Y axesrespectively, described with reference to FIG. 6 couple the decodedoutputs of decoders 114 and 116 to the reference voltages and rampswhereby the appropriate voltage selection is made for coupling to theanalog circuitry for generation of the required stroke deflectionvoltages.

The vector length approximation provided by the length calculator 42 iscoupled to the ramp generator 122 to provide ramps with a time durationdirectly proportional to the calculated vector length, thus achievingconstant writing speed. The vector endpoints determinative of the Xposition are coupled to subtractor 144 from the X start register 106 andthe X end register 108, which subtractor derives the change in thevector position:

The Y position end points are coupled to subtractor 146 from the Y endpoint register 1 l2 and the Y start register 1 10 to obtain the changein vector length in the Y direction The outputs of subtractors 144 and146 are coupled to a comparator 148 where A X is compared with A Y andto two storage registers 150 and 152 in the X and Y axis respectively.If A Y is greater than or equal to AX, then A Y is coupled to register150 and the quantity A X A A X) is derived. If A X is greater than A Y,then the output of comparator 148 is coupled to storage register 152 toderive quantity 1% A Y (A Y) and the outputs of both registers 150 and152, which are conventional ten bit storage registers, is coupled to anadder 154 of conventional design in which the quantities:

AX+%AYforAX AY AY+%AXforAY z AX are derived and coupled to an ll-bitstorage register 156 for storage prior to coupling to the ramp generator122 to develop the generated ramp transition time.

The error due to this approximation is.a function of vector angle, andthe worst case error is sufficiently small such that a worst casebrightness deviation of plus or minus 6 percent results, which deviationis imperceptible to the human eye. I

Referring now to FIG. 5, the ramp generator is illustrated generally at48. The ramp generator produces a linear voltage oiitput V (t) which isclamped at zero volts and at a reference voltage Vref. Of; course, theoutput could, if desired, be clamped to two different referencevoltages. The ramp generator receives digital length data from the linelength calculating network 42 via 10 lines, L, through L which lengthdata enables or disables a bank of binary weighted capacitors, C,through C four of which are shown at 200, 202, 204 and 206. Of course,any number of digital length inputs, Ly to L may be used, with eithermore or less than 10 binary weighted capacitors. The binary weighting is2C, 2C, 2 C Z C, with the enabled capacitance values being a function ofvector length for effecting the determination of the transition time ofthe generated ramp in accordance with the following equatrons:

V0 (y) (I/Ct) y constant V and n) y Cl KiLv and y KLv where r= ramptransition time C, enabled capacitance K constant of proportionality Lvvector length Vr= reference voltage I constant current source Thus, theramp output signal which equals V,(t],y) and its inversion V, [l (!/y)]are used as reference signals for the digital-to-analog converters. Withthe output V (t) clamped between two reference voltages, the transitiontime is proportional to the calculated line length in accordance with i=yk la The two alternative methods of making the transition time yproportional to the vector line length Lv are controlling I as afunction of i 1/ W0 D) and controlling C as a function of VA X K Y Theformer is difficult to achieve since the computation .practical usefulrange of control may be extended beyond 100,000zl (50 pf to 5 mf).Therefore, this method of control is particularly suitable to a binaryweighting system and increases the range of constant transition linelengths that can be generated.

Transistors 208 and 210 charge the binary weighted capacitors witheither +V or -V while diode networks 212 through 218 provide binaryselection. For a given vector length (Lv) digitally inputted in binaryform at Lvl through Lvn, where n is 10, for example, the appropriate FETswitches 220, 222, 224 and 226 will close, which represents the chargeacross the 10 capacitors, developing a total capacitance of C, where C=2 Lvo C+2 Lv1+ 2 Lv which may be generally expressed as whereTransistors 208 and 210 are initializing transistors which initializethe charge on the binary weighted capacitors before each stroke. Controlsignals from the logic network are supplied via lines 228 and 230 to thebases of transistors 208 and 210 respectively, which signals turn theinitializing transistors ON and OFF in accordance with the digitalinput, with a logical one being ON and a logical zero being OFF.

The outputs of the FET switches 220 through 226 are summed at node 232,which voltage is the analog representation of the total summedcapacitance. the value of which is representative of the length of thestroke to be generated. This summed capacitance is coupled to a pair ofalternately switched positive and negative current sources +l and lrespectively, the switching being provided by a transistor switch 234which is driven from the logic circuitry via line 236 to provide theoutput ramp function. The ramp is coupled through a buffer, such as anemitter follower 240,

which couples the high impedance input to two low impedance comparators242 and 244 of conventional design. Comparators 242 and 244 compare theoutput of emitter follower 240 to a reference voltage Vr and to zerorespectively, and transistors 246 and 248 clamp the comparators to thesevalues, thus comparing the clamping voltage with the ramp voltage. Whenthe ramp voltage exceeds the compared voltage, transistors 246 and 248switch ON to hold the output within the clamping limits. The output ofcomparators 242 and 244 are coupled to the blanking and unblankingcircuitry respectively, and the ramp generator output appears at none250.

Referring now to H6. 6, the decoder and four position switch isillustrated for the X axis generally at 260. As the Y-axis decoder andfour position switch is identical, only the X-axis circuit isillustrated. The X axis decoder 260 compares each bit of the initial Xposition (Xs) with each bit of the final X position (Xe) in four NANDgates 262, 2 64, 266 and 268 which receive their inputs from the X and Xregisters 106 and 108 via lines 270 through 276. The decoder outputconsists of four output lines for each bit of the input length, whichlines are coupled through emitter followers 278, 280, 282 and 284 tofour FET switches 286, 288, 290 and 292.

The four possible combinations which may be switched to thedigital-to-analog ladder network 294 of which only a portion is shown,are:

X =X =0 X0 X l X0=0,X!=1 X0: l,X 0

This data is switched via lines 296, 298, 300 and 302 respectively, andthe activated line couples in one of the four reference signals into theleg of the digital-toanalog network 294 representing the value andweight of the decoded bit. The reference signals coupled via lines 298and 300 are derived from the ramp generator 48 and invertor 52, andcomprise the positive and negative going ramps Vr (t)/(1') and Vr [l(t/r)] respectively, while lines 296 and 302 couple zero volts and Vrrespectively to the four position switch.

As is apparent on line 296, X O and X 0, therefore the starting andending vector position are a logical 0, and the reference 0V is switchedinto the digital-to-analog leg.

When X 0 and X, I, that bit increases from 0" to 1 during the stroketransition time y, hence the rampgenerator reference output V0(t) Vr(t)/('r) is switched into the digital-to-analog leg via line 298.

When X 1 and X 0," that bit will decrease during the transition time yfrom l to O," hence the inverter reference output V0(t) Vr [l (t/1')]will be switched into the digital-to-analog leg via line 300.

Similarly, when X 1 and X l the starting and ending position for thatbit are a logical l therefore, the reference voltage Vr is switched intothe digital-to-analog leg via line 302.

It is apparent that the positive and negative going ramps and the tworeference voltage levels are determinative of the stroke positioning inthe X axis. While the D/A ladder is illustrated only for the X l and X 1l condition, the other ladders are identical, and the composite outputis summed in an X summing amplifier 304, from which the analog voltageVx (r) X I /r)] X; (t/r) is applied to the X axis CRT deflectioncircuitry. Of course, the circuitry for the Y axis is identical, and thesignal applied to the Y axis Y deflection circuitry is Vy (t) Y0 [(1(t/r)] 1 (#1).

The digital-to-analog output is the binary weighted sum of each of thereference inputs as determined by the decoder NAND switches whichestablishes the amplitude change of the digital-to-analog converter.When a ramp is generated, digital-to-analog outputs produce the X and Ycoordinates of the vector to be generated.

While particular embodiments of the invention have been shown anddescribed, various modifications thereof will be apparent to thoseskilled in the art. For

example, alphanumeric characters may be generatedby expansion of thelogic rather than vectors, and therefore it is not intended that theinvention be limited to the disclosed embodiments or details thereof anddepartures may be made therefrom within the spirit and scope of theinvention as defined in the appended claims.

What is claimed is: l. A visual display system comprising: means forgenerating digital vector end point data; means for converting saiddigital data to analog signals having a time duration that is directlyproportional to the length of said vector; means coupled to saidconverting means for generating a visual display at a constant writingrate; means coupled to said means for generating digital vector endpoint data for generating stroke length data; means for generating avoltage ramp with a time duration directly proportional to said derivedstroke length; means for switching said voltage ramp into saiddigital-to-analog converting means in accordance with said digital endpoint data such that a constant transition rate vector is generated onsaid visual display; and wherein said means for generating stroke lengthdata comprises a hypotenuse approximation circuit which comprises: afirst subtractor for subtracting the X component of a starting point ofsaid vector from the X component of an end point of said vector; asecond subtractor for subtracting the Y component of a starting point ofsaid vector from the Y component of an end point of said vector; acomparator for comparing the outputs of said first and said secondsubtractors; first combining means responsive to an output of saidcomparator for providing an output equal to the sum of an output of saidfirst subtractor with one-half the output of said second subtractor whenthe output of said second subtractor is greater than the output of saidfirst subtractor; second combining means responsive to an output of saidcomparator for providing an output equal to the sum of an output of saidsecond subtractor with one-half the output of said first subtractor whenthe output of said first subtractor is greater than the output of saidsecond subtractor; and

means for coupling the output of said first combining means and theoutput of said second combining means to said ramp generating means, theoutput of said first combining means being the hypotenuse approximationwhen the output of said second subtractor is greater than the output ofsaid first subtractor, the output of said second combining means beingthe hypotenuse approximation when the output of said first subtractor isgreater than the output of said second subtractor. 2. A vector generatorcomprising: means for receiving digital vector end point data; meansforconverting said digital end point data into a digital quantityrepresentative of the vector length; means for generating controlvoltages responsive to said digital quantity, the time duration of saidcontrol voltages being proportional to the vector length;digital-to-analog means for converting said control voltages to-analogsignals in accordance with said digital end point data; means fordisplaying said analog signals as vectors at a constant writing rate;said means for receiving digital vector end point data comprising firstand second storage registers for receiving vector starting point dataand vector end point data for a first axis, said vector end pointreceiving means further comprising third and fourth storage registersfor receiving vector starting point data and vector end point data for asecond axis, said second axis being orthogonal to said first axis; saidmeans for converting said digital end point data into a digital quantityrepresentative of said vector length comprising: means for digitallyapproximating the function substituting therefor the quantity AX+VzA Ywhen AX AY and AY+%AX when AY z AX where A X is the absolute value ofthe difference between the vector end point and starting point in the Xaxis and A Y is the difference between the vector end point and startingpoint in the Y axis; and wherein said digital approximation meansincludes: first and second subtractors for deriving the quantities A Xand A Y, from said first and second and said third and fourth storageregisters, respectivey; a comparator for comparing the outputs of saidfirst and second subtractors; first means for storing the output of saidcomparator when A Y .2 A X;

second means for storing the output of said comparator when A X A Y;

means for adding the outputs of said first and second storage registersto derive said digital approximation; and

means for storing said digital approximation.

3. In combination:

means for receiving components of data of a vector to be displayed, saiddata having an X component and a Y component of a start point of saidvector, and said data having an X component and a Y component of an endpoint of said vector;

means for generating a ramp signal, said ramp generating means includingmeans for inverting said ramp signal;

means coupled to said data receiving means and said ramp generationmeans for multiplying said start point data and said end point data byrespectively said inverted ramp signal and said ramp signal;

means coupled to said multiplying means for combining output signals ofsaid multiplying means for displaying said vector;

a hypotenuse approximation circuit coupled to said ramp generation meansfor varying the rate of change of said ramp signal, said hypotenuse approximation circuit comprising: first and second subtractors forderiving the quantities A X and A Y from said X and said Y component ofsaid start point and said X and Y component of said end point;

a comparator for comparing the outputs of said first and said secondsubtractors;

first means coupled to said comparator for obtaining one-half the outputof said first subtractor when A Y a A X;

second means coupled to said comparator for obtaining one-half theoutput of said second subtractor when A X A Y;

means for adding the outputs of said first and said second subtractorsto the outputs of said first and said second obtaining means to derive asignal having a value approximating a hypotenuse from said start pointto said end point.

4. In a system employing a ramp generator for generating a display ofvectors each of which are drawn from a start point to an end point, thestart point and the end point each being described by an X component anda Y component, a hypotenuse approximation circuit coupled to the rampgenerator for varying the rate of change of ramp signals provided bysaid ramp generator, said hypotenuse approximation circuit comprising:

first and second subtractors for deriving the quantities A X and A Yfrom said X components and said Y components of said start and said endpoints;

a comparator for comparing the outputs of said first and said secondsubtractors; first means coupled to said comparator for obtainingone-half the output of said first subtractor when A Y AX;

second means coupled to said comparator for obtaining one-half theoutput of said second subtractor when A X A Y;

means for adding the outputs of said first and said ing a valueapproximating a hypotenuse from said second subtractors to the outputsof said first and start point to said end point. said second obtainingmeans to derive a signal hava

1. A visual display system comprising: means for generating digitalvector end point data; means for converting said digital data to analogsignals having a time duration that is directly proportional to thelength of said vector; means coupled to said converting means forgenerating a visual display at a constant writing rate; means coupled tosaid means for generating digital vector end point data for generatingstroke length data; means for generating a voltage ramp with a timeduration directly proportional to said derived stroke length; means forswitching said voltage ramp into said digital-toanalog converting meansin accordance with said digital end point data such that a constanttransition rate vector is generated on said visual display; and whereinsaid means for generating stroke length data comprises a hypotenuseapproximation circuit which comprises: a first subtractor forsubtracting the X component of a starting point of said vector from theX component of an end point of said vector; a second subtractor forsubtracting the Y component of a starting point of said vector from theY component of an end point of said vector; a comparator for comparingthe outputs of said first and said second subtractors; first combiningmeans responsive to an output of said comparator for providing an outputequal to the sum of an output of said first subtractor with one-half theoutput of said second subtractor when the output of said secondsubtractor is greater than the output of said first subtractor; secondcombining means responsive to an output of said comparator for providingan output equal to the sum of an output of said second subtractor withone-half the output of said first subtractor when the output of saidfirst subtractor is greater than the output of said second subtractor;and means for coupling the output of said first combining means and theoutput of said second combining means to said ramp generating means, theoutput of said first combining means being the hypotenuse approximationwhen the output of said second subtractor is greater than the output ofsaid first subtractor, the output of said second combining means beingthe hypotenuse approximation when the output of said first subtractor isgreater than the output oF said second subtractor.
 2. A vector generatorcomprising: means for receiving digital vector end point data; means forconverting said digital end point data into a digital quantityrepresentative of the vector length; means for generating controlvoltages responsive to said digital quantity, the time duration of saidcontrol voltages being proportional to the vector length;digital-to-analog means for converting said control voltages to analogsignals in accordance with said digital end point data; means fordisplaying said analog signals as vectors at a constant writing rate;said means for receiving digital vector end point data comprising firstand second storage registers for receiving vector starting point dataand vector end point data for a first axis, said vector end pointreceiving means further comprising third and fourth storage registersfor receiving vector starting point data and vector end point data for asecond axis, said second axis being orthogonal to said first axis; saidmeans for converting said digital end point data into a digital quantityrepresentative of said vector length comprising: means for digitallyapproximating the function Square Root ( Delta X)2 + ( Delta Y)2substituting therefor the quantity Delta X + 1/2 Delta Y when Delta X >Delta Y and Delta Y + 1/2 Delta X when Delta Y > or = Delta X whereDelta X is the absolute value of the difference between the vector endpoint and starting point in the X axis and Delta Y is the differencebetween the vector end point and starting point in the Y axis; andwherein said digital approximation means includes: first and secondsubtractors for deriving the quantities Delta X and Delta Y, from saidfirst and second and said third and fourth storage registers,respectively; a comparator for comparing the outputs of said first andsecond subtractors; first means for storing the output of saidcomparator when Delta Y > or = Delta X; second means for storing theoutput of said comparator when Delta X > or = Delta Y; means for addingthe outputs of said first and second storage registers to derive saiddigital approximation; and means for storing said digital approximation.3. In combination: means for receiving components of data of a vector tobe displayed, said data having an X component and a Y component of astart point of said vector, and said data having an X component and a Ycomponent of an end point of said vector; means for generating a rampsignal, said ramp generating means including means for inverting saidramp signal; means coupled to said data receiving means and said rampgeneration means for multiplying said start point data and said endpoint data by respectively said inverted ramp signal and said rampsignal; means coupled to said multiplying means for combining outputsignals of said multiplying means for displaying said vector; ahypotenuse approximation circuit coupled to said ramp generation meansfor varying the rate of change of said ramp signal, said hypotenuseapproximation circuit comprising: first and second subtractors forderiving the quantities Delta X and Delta Y from said X and said Ycomponent of said start point and said X and Y component of said endpoint; a comparator for comparing the outputs of said first and saidsecond subtractors; first means coupled to said comparator for obtainingone-half the output of said first subtractor when Delta Y > or = DeltaX; second means coupled to said comparator for obtaining one-half theoutput of said second subtractor when Delta X > Delta Y; means foradding the outputs of said first and said second subtractors to theoutputs of said first and said second obtaining means to derive a signalhaving a value approximating a hypotenuse from said start point to saidend point.
 4. In a system employing a ramp generator for generating adisplay of vectors each of which are drawn from a start point to an endpoint, the start point and the end point each being described by an Xcomponent and a Y component, a hypotenuse approximation circuit coupledto the ramp generator for varying the rate of change of ramp signalsprovided by said ramp generator, said hypotenuse approximation circuitcomprising: first and second subtractors for deriving the quantitiesDelta X and Delta Y from said X components and said Y components of saidstart and said end points; a comparator for comparing the outputs ofsaid first and said second subtractors; first means coupled to saidcomparator for obtaining one-half the output of said first subtractorwhen Delta Y > or = Delta X; second means coupled to said comparator forobtaining one-half the output of said second subtractor when Delta X >Delta Y; means for adding the outputs of said first and said secondsubtractors to the outputs of said first and said second obtaining meansto derive a signal having a value approximating a hypotenuse from saidstart point to said end point.